VHDL – Dr. Ranga Vemuri

Universal State Machine modeled in VHDL. Built in the design style of first designing a behavioral model and test benches, and then piece by piece implementing each component at the gate level.

Project Files

This is a fairly basic project, but is a good demonstration of some of the uses of VHDL. This is a hardware description of a gate level model of a universal state machine. As input, the state transition table is read into the machine, and then it makes “decisions” based on the inputs and current state. All buses in this design are scale-able, so any (memory permitting) number of states and inputs may be modeled. The gates in the library are NOT, AND, OR, XOR, and a tri-state buffer. From these gates all components are designed.

Included at the link are all the .vhd files associated with the project. The usm_gate.vhd file is the top level of the design. Also in that file are a few test benches demonstrating the use of the USM.