# VLSI Projects

## VHDL USM

Aug 12th

VHDL – Dr. Ranga Vemuri

Universal State Machine modeled in VHDL. Built in the design style of first designing a behavioral model and test benches, and then piece by piece implementing each component at the gate level.

This is a fairly basic project, but is a good demonstration of some of the uses of VHDL. This is a hardware description of a gate level model of a universal state machine. As input, the state transition table is read into the machine, and then it makes “decisions” based on the inputs and current state. All buses in this design are scale-able, so any (memory permitting) number of states and inputs may be modeled. The gates in the library are NOT, AND, OR, XOR, and a tri-state buffer. From these gates all components are designed.

Included at the link are all the .vhd files associated with the project. The usm_gate.vhd file is the top level of the design. Also in that file are a few test benches demonstrating the use of the USM.

## Low Power Experiments

Aug 12th

Cell based low power experiments:

Measuring Leakage, Dynamic, and Crossover currents/power usage.

Interconnets experiments:

Wire tapering, wire capacitance.

## Partitioning Tool – KL Algorithm

Aug 12th

VLSI Design Automation – Dr. Ranga Vemuri

This is a VLSI partitioning tool using the KL algorithm to solve the bipartitioning problem. It takes a netlist as input, attempts to partition it into 2 sets with a minimum cutset. The minimization is of the number of connections between the resulting netlists. The algorithm implemented is the Kernighanâ€“Lin (KL) algorithm.

I won’t try to do better than the Wikipedia article, but here is a basic description of the algorithm and its application to this problem:

The KL algorithm works by first dividing the graph into two sets with an equal number of vertices (presumably randomly, unless there is some prior knowledge). A cost is then calculated for each vertex. The cost is the weighted external connections (an edge connecting a vertex to the other set) minus the number of weighted internal connections (an edge connecting to a vertex in the same set). This difference is called the D value. The greater the D value, the greater the benefit of switching the vertex to the other set.

The KL algorithm simply proceeds by sorting the vertices in each set by D value, and then swapping them two at a time (one from each set). After each swap, the two that just participated in the swap are marked as no longer eligible for more swaps this pass. The D values are recalculated for all eligible vertices, and the process begins again. They are sorted, and the highest beneficial swap from each set is chosen. This continues until there are no more beneficial swaps. Then all nodes are marked eligible again, and another pass is attempted. This continues until more passes cannot improve the cost of the cut. This is the basic thinking behind the algorithm, it will actually proceed as follows:

- Step 1: G(V,E) is graph of V vertices and E edges.

(A,B) is initial partition of V, such that A and B are equal sized subsets with no overlap and their union covering all of V. - Step 2: Compute Dv = Ev – Iv for all v in V.
- Step 3: Choose ai from A and bi from B that maximizes gi = Dai + Bai + 2caibi. The final term is the connection between the two, if it exists. Add pair (ai, bi) to queue. Remove ai and bi from allowable swaps.
- Step 4: If there are no more eligible nodes for swap, goto Step 5.

Else, recalculate D values for remaining eligible nodes, goto Step 3. - Step 5: find k to maximize the partial sum of gi from i to k in the queue. If total sum G is greater than 0, perform all swaps (a1, …, ak with b1, …, bk), and goto Step 2. Else, end.

This is a deterministic heuristic.

This was one of my first projects writing software from scratch, and it can definitely be seen from my design. I was pretty new as far as my C++ skill, so there is a lot of room for improvement in the design (as far as object orientation). However, it does perform correctly. I learned a lot from this project, and I think improvement can be seen from this project to the next I did, the Placement/Routing tool.

## Placement/Routing Tool

Aug 12th

VLSI Design Automation Placement/Routing Tool

All cells are the same size, and contain 4 terminals (blackbox representation).

Given a netlist, minimize the area necessary for placement.

Netlist -> Initial Placement -> Simulated Annealing with Route Approximation -> Routing -> Design

## JTAG BSD Design

Aug 12th

Boundary Scan Design

Completed RTL Design -> Scan Chain Addition -> JTAG Boundary Scan Addition

ATPG -> Test Coverage

## Northeast Route Checker

Aug 12th

VLSI Physical Design Project

Design of Algorithm -> Physical Design -> Testing/Validation